altera


How to use new component created in Qsys to vectorize/group together many signals


In the Qsys, I am using twelve input parallel ports (lets name them pio1 to pio12), each port is 12 bits. These parallel ports obtain values from the vhdl block in Quartus schematic. In the schematic bdf, I can see pio1 to pio12 from the nios ii system symbol so I can connect these pios to other blocks in my bdf.
My question is, how to vectorize these pio1 to pio12? Instead of seeing all twelve pios one line by one line coming out from the Nios system symbol, what should I do in order to group all these twelve pios so that I only see one instead of twelve? From the one pio that I see, I can name it pio[1..12][1..12], the first bracket means pio1 to pio12, the second bracket means bit 1 to bit 12 because each parallel port has 12 bits.
I have created a new component in Qsys using this pio_helper.vhd file,
The pio_helper.vhdl file is as follows:
entity pio_helper is
port(
pio1 : in std_logic_vector(11 downto 0);
pio2 : in std_logic_vector(11 downto 0);
pio3 : in std_logic_vector(11 downto 0);
pio4 : in std_logic_vector(11 downto 0);
pio5 : in std_logic_vector(11 downto 0);
pio6 : in std_logic_vector(11 downto 0);
pio7 : in std_logic_vector(11 downto 0);
pio8 : in std_logic_vector(11 downto 0);
pio9 : in std_logic_vector(11 downto 0);
pio10 : in std_logic_vector(11 downto 0);
pio11 : in std_logic_vector(11 downto 0);
pio12 : in std_logic_vector(11 downto 0);
piomerge : out std_logic_vector(143 downto 0)
);
end pio_helper;
architecture behavior of pio_helper is
begin
piomerge(11 downto 0) <= pio1;
piomerge(23 downto 12) <= pio2;
piomerge(35 downto 24) <= pio3;
piomerge(47 downto 36) <= pio4;
piomerge(59 downto 48) <= pio5;
piomerge(71 downto 60) <= pio6;
piomerge(83 downto 72) <= pio7;
piomerge(95 downto 84) <= pio8;
piomerge(107 downto 96) <= pio9;
piomerge(119 downto 108) <= pio10;
piomerge(131 downto 120) <= pio11;
piomerge(143 downto 132) <= pio12;
end behavior;
I got the following errors, I have few questions:
I assume I wont have clock and reset signals, cause this is purely data transfer
writebyteenable_n appears 12 times (only once is allowed), but I have 12 pios...what changes to be made?
Warning: avalon_slave_0: Signal writebyteenable_n appears 12 times
(only once is allowed) Error: avalon_slave_0: Interface must have an
associated clock Error: avalon_slave_0: Interface must have an
associated reset Error: avalon_slave_0: Interface must have an
associated clock.
The warning and error you see is because you haven't defined this connections as conduit export, the signals are configured as avalon slave signals.
Go to edit your component in Qsys, Signals tab and set the signals as conduit_end, then in the next tab click the button "Remove dangling connections". This might solve the problem you have with the warning and error.
For the question about the grouping of pins I don't know if it's possible to do so.

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