altera


How can I debug Schematic File separately from my project file in Quartus?


I have a Quartus II project configured to be used with Cyclone II. And I have a design I'm trying to debug using simulation facilities. It would be perfect if I could insert output pin after every symbol block in my design to see where I'm messing up, but if I do so, Quartus complains that it cannot fit the design on the device. How can I overcome this?
Is there a way to create some-kind-of-generic-project, not tied to a device, so I could test the logic?
You getting this error, when you're trying to perform full Compilation process (design compilation, timing analysis etc.). But it's not required if you simply want to simulate how your logic is going to work.
Solution:
Open Tasks Window (View > Utility Windows > Tasks).
In the Existing Flow list, you can see default flows: Compilation, Gate Level Simulation, RTL Simulation, Full Design).
Select RTL Simulation. This flow consists of only two tasks: Analysis & Elaboration and simulation.
When you perform only this two tasks, Quartus is not checking (fitter is not being used) if your logic will fit into the device.

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